The performance of integrated circuits has been increasing with the progress in scaling. Meanwhile, the leakage current increases while a transistor such as MOSFET, namely an elementary device forming integrated circuits, is at off state. Resulting increase in power consumption has recently been inhibiting further improvement in performance based on scaling. Under such circumstances, an attempt has been made intensively to eliminate or decrease off-leakage current by interrupting the power for a memory circuit while the memory circuit is not performing memory access. In this case, it is necessary to restore the state of the memory circuit after the power is turned on again. This is done by backing up (storing) the data of the memory circuit into another memory element, which has long data retention time before the power is turned off.
As the memory elements described above, various memories using the magnetic tunnel junction (MTJ), the resistance random access memory (ReRAM), the phase-change random access memory (PCRAM), etc. have been proposed.
A semiconductor memory device, which can store data without power supply and write and read data at high speed, will be used for on-chip cache memory in logic LSIs in future, and thus is attracting attention as a technology capable of decreasing the power for logic LSIs significantly.
In particular, the memory that uses the resistance change-type MTJ device as the memory element is the most promising candidate, since the stable memory operation is ensured even if the memory cell is downsized owing to its high endurance for switching and the future miniaturization of MTJ devices.
A spin-injection-type MTJ device (spin-transfer-torque (STT)-MTJ device), which can perform switching of a free layer by changing the direction of the current fed to the MTJ device without applying an external magnetic field, has been realized. A so-called MTJ/CMOS hybrid integrated circuit, which combines the MTJ device or STT-MTJ device with a CMOS integrated circuit, is one of the most promising candidates for ultra-low-power LSI.
However, the writing data at high speed to a memory device having long data retention time has not been put into practical use due to general problems described below.
Patent Literature 1 and Non-Patent Literature 1 disclose nonvolatile latch circuits.
FIG. 132 is a circuit diagram of a nonvolatile latch circuit 800 disclosed in Non-Patent Literature 1. As shown in this figure, the nonvolatile latch circuit 800 disclosed in Non-Patent Literature 1 includes: a bistable circuit 810 wherein two inverters 801, 802 are connected in a shape of a ring; and MTJ devices 803, 304 respectively connected to the input and the output of the bistable circuit 810. The nonvolatile latch circuit 800 in Non-Patent Literature 1 assumes the operation based on reversal of MTJ devices 803, 804. In addition, in this nonvolatile latch circuit 800, a latch made of a CMOS circuit and MTJ devices 803, 804 are connected via a MOSFET for switching, and by turning it on or off, the write to the MTJ devices 803, 304 is controlled (See Non-Patent Literature 1, FIG. 8).
FIG. 133 is a block diagram showing the structure of MTJ/CMOS hybrid integrated circuit of the conventional example 1. As shown in the figure, with the MTJ/CMOS hybrid integrated circuit in the conventional example 1, the data is written into the MTJ device in every cycle, which requires the MTJ device to have the operation frequency of the CMOS. Furthermore, in order to write data to the MTJ device at high speed, the write voltage must also be increased.
FIG. 134 is a block diagram showing the structure of an MTJ/CMOS hybrid integrated circuit in the conventional example 2. As shown in this figure, the MTJ/CMOS hybrid integrated circuit in the conventional example 2 uses CMOS only. However the conventional MTJ/CMOS hybrid integrated circuit can store data to the MTJ device before power control (called PG) is performed. In this case, low-power operation is allowed. Even if the operation is performed at high speed, the storage error of the MTJ device can be suppressed because this circuit does not require high-speed operation for the MTJ device. However, a peripheral circuit for control is required for the MTJ device to store data or reload the stored data.
However, the operation frequency of the disclosed MTJ/CMOS hybrid integrated circuit is not as fast as CMOS LSI (See Non-Patent Literatures 3, 4). With the MTJ device, when the switching speed increases to several hundred MHz, the increases of the switching error and the switching current of the MTJ device occur.
FIG. 135 is a circuit diagram showing the basic structure of a nonvolatile latch 850 disclosed by the present inventors et al. in Non-Patent Literature 2. As shown in FIG. 135, the nonvolatile latch 850 includes: a first latch 860; spin-injection-type MTJ devices 865, 866 connected to the first latch 860; and a second latch 870 connected to the spin-injection-type MTJ devices 865, 866. The data is written into the spin-injection-type MTJ devices 865, 866 at the operation frequency lower than that of the first and/or the second latch 860, 870.